# Error en VHDL extraño



## Catrip (Oct 13, 2010)

Les mando mi código en VHDL de parte del generador de direcciones de memoria, al momento de compilar me lanza distintos errores:


```
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity LectEsc is
	port(clk	    : in  std_logic;
	     PRO, RW	    : in  bit;
       	     RD, WR, INCDIR : out bit
	);
end LectEsc;

architecture RTL of LectEsc is
 	signal state, next_state: bit; -- INI = 1, MEM = 0
	attribute syn_encoding : string;
	attribute syn_encoding of state : signal is "onehot";
begin

	process (clk)
 	begin
		if rising_edge(clk) then
			state <= next_state;
		end if;
	end process;
	
	process (state, PRO, RW)
	begin
		case state is
			when '0' =>	-- MEM
			
				if PRO = '1' then
					if RW = '1' then
						INCDIR <= '0';
						RD   <= '1';
						WR  <= '0';

						next_state <= '0'; -- MEM
					else
						INCDIR <= '0';
						RD   <= '0';
						WR  <= '1';

						next_state <= '0'; -- MEM
					end if;
				else
					INCDIR <= '1';
					next_state <= '1';
				end if;

			when '1' =>	-- INI
				
				if PRO = '1' then
					next_state <= '0'; -- MEM
				else
					next_state <= '1'; -- INI
				
				end if;
							
			when others =>
				next_state <= '1';	-- INI
				
		end case;
		
	end process;
	
end RTL;
```

El error que muestra es:

Updating: Fit Design

Starting: 'C:\ispTOOLS\ispsys\bin\fit.exe lecturaescritura.tt2 -dev P22V10 -str -gui -err automake.err'

FIT  Generic Device Fitter
Copyright(C), 1992-2000, Lattice Semiconductor Corporation. All rights reserved
Portions Copyright(c), 1992-1999, Vantis Corporation
Portions Copyright(C), 1993-1998, Data I/O Corporation
Portions Copyright(C), 1997-1998, MINC Washington Corporation
Portions Copyright(C), Alan Phillips, Lancaster University Computer Centre 1992-1998
Input file: 'lecturaescritura.tt2'
Device 'P22V10'
Note 4068: Signal INCDIR cannot be assigned (to pin 23) because
the register type of 'INCDIR' pin 23 is invalid.

Note 4068: Signal WR cannot be assigned (to pin 23) because
the register type of 'WR' pin 23 is invalid.

Note 4068: Signal RD cannot be assigned (to pin 23) because
the register type of 'RD' pin 23 is invalid.

Design does NOT fit

Done: failed with exit code: 0001.

Y su respectiva Carta ASM es la siguiente:







[/CENTER

Les pido que me ayuden a corregir dicho problema...​


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## Ivaraf (Feb 13, 2012)

hola, oye podrias decirme por que sale ste error, estoy en el mismo problema. :/


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