use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity CAR is //definer la eentidad carro
PORT (IN1,IN2,CLK:IN STD_LOGIC; Q1,Q1N,Q2,Q2N:OUT STD_LOGIC);// entradas y salidas de la entidad
end CAR
Architecture CAR_CONTROL of CAR is
signal (QT,fin: STD_LOGIC;cont:integer range o to 99000)
begin
process (IN1,IN2,CLK,fin,cont)
begin
if (rising_edge(IN1) or RISING_EDGE(IN2)) then
QT<= NOT QT;
if QT=1 then
Q1<=0;
Q1N<=0;
Q2<=0;
Q2N<=1;
else //QT=0
Q2<=0;
Q2N<=0;
Q1<=0;
Q1N<=1;
end if
cont<=3000;
fin<=0;
CICLO DE ESPERA
while fin = 0 loop
if ( clk'event and clk='1') then
cont<=cont -1;
if cont= '0'
fin<='1';
end if
end if
end loop
else
Q1<=1;
Q2<=1;
Q1N<=0;
Q2N<=0;
end if
library ieee;
use ieee.std_logic_1164.all;
entity contador is port (clk: in std_logic;
rst: in std_logic;
q: inout std_logic_vector (3 downto 0));
end contador;
architecture cuenta of contador is
begin
process (clk,rst) begin
if (rst'event and rst = '0') then
q<= "0000";
if (clk'event and clk = '0') then
q <= q+1;
end if;
end if;
end process;
end cuenta;library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port (
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (3 downto 0)
);
end counter;
architecture count of counter is
signal cnt : std_logic_vector (3 downto 0);
begin
process (clk,rst) begin
if (rst = '0') then
cnt <= (others => '0');
elsif (clk'event and clk = '0') then
cnt <= cnt + 1;
end if;
end process;
q <= cnt;
end count;
